Logic Checks Group on the S2 // Logic Tab

Use the commands in this group to check, among other things, redundancy, circular logic, and reverse logic.

Field	Description
Redundancy Index	This displays only relationships with redundant logic. A redundant link occurs when, in addition to the link in question, there is a more detailed logic link between the same two activities. For example, a link from Activity A to activity C is made redundant by an existing link from Activity A to Activity B and another one from Activity B to Activity C.
Circular Logic	This displays only relationships which are part of circular logic. Circular links often occur in multi-project schedules. For example, a circular link would be a link from A to B and then another link from B to A. Circular logic analysis checks for paths of activities that loop back on themselves. This is a big concern in multi-project environments (for example, multiple Primavera files that reference each other) where circular logic checks can otherwise go undetected.
Open Ends	This displays only relationships with an open end. Open ends analysis checks for any activities that are missing either predecessors or successors, causing the activity to be "open ended."
Logic on Summaries	This displays summary tasks that have logic. Logic links on summaries are typically viewed as a poor scheduling technique, as the summary is not a true activity but rather a grouping of activities. Logic should be tied to the actual work in the schedule.
Out of Sequence	This displays tasks and relationships that have our of sequence progress. This analysis checks for clashes between logic progress/status updates. Out of sequence errors occur between activities when the successor activity status contradicts the logic with its predecessor. For example, a successor activity starting before its FS predecessor has started.
Reverse Logic	This displays only tasks that have reverse logic. Reverse logic errors occur when the start of a successor activity starts before the start of the predecessor. Typically caused by negative lags (leads), these reverse logic errors should be avoided at all costs.